Electrical Engineering Seminar Abbas Rahimi 2015-04-07
From Margaret Hastings on April 8th, 2015
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From Variability-Tolerance to Approximate Computing via Parallel Processing
Variation in performance and power across manufactured parts and their operating conditions is an accepted reality in modern microelectronic manufacturing processes with geometries in nanometer scales. Variability causes timing errors in computing systems that are typically avoided by ultra-conservative guardband. We focus on reducing guardband and mitigating variability effects by exploiting parallel processing. This naturally leads to an emerging area of approximate computing.We investigated separate methodological approaches to predict-and-prevent, to detect-and-correct, and finally, to accept timing errors; we evaluated their implications on cost, performance and quality of the output results. We devise an arsenal of software techniques and memoization-based optimizations for improving cost and scale of these approaches in massively parallel computing units, such as those found in GP-GPUs and other clustered many-core accelerators. The result was a framework for cross-layer (i.e., across software stack) and hybrid (i.e., across hardware and software) resiliency. This enabled us to combine methods for correcting error and accepting error to devise a new method for approximate error correction across the hardware/software interface viamemoization. That is, ensuring safety of error-tolerance through a set of rules verified by a combination of design-time and runtime constraints. Spatial and temporal memorization, with the use of memristive memory blocks, significantly reduce the cost of resiliency and enhance the range of variability-induced timing errors that can be mitigated at very low cost.
Bio: Abbas Rahimi is currently a fifth year Ph.D. candidate in the Department of Computer Science and Engineering at the University of California, San Diego. He is working with Professor Rajesh Gupta and Professor Luca Benini. Since June 2010, he has also been with the Microelectronic Group at the University of Bologna and the Integrated Systems Laboratory at the Swiss Federal Institute of Technology Zurich. His research interests are in the massively parallel integrated architectures, approximate computing, resilient system design, design for robustness, embedded systems, and on-chip interconnections. Mr. Rahimi received the Best Paper Candidate at 50th IEEE/ACM Design Automation Conference. He received the B.S. degree in computer engineering from the School of Electrical and Computer Engineering at the University of Tehran, in March 2010.
Host: Gu-Yeon Wei
Variation in performance and power across manufactured parts and their operating conditions is an accepted reality in modern microelectronic manufacturing processes with geometries in nanometer scales. Variability causes timing errors in computing systems that are typically avoided by ultra-conservative guardband. We focus on reducing guardband and mitigating variability effects by exploiting parallel processing. This naturally leads to an emerging area of approximate computing.We investigated separate methodological approaches to predict-and-prevent, to detect-and-correct, and finally, to accept timing errors; we evaluated their implications on cost, performance and quality of the output results. We devise an arsenal of software techniques and memoization-based optimizations for improving cost and scale of these approaches in massively parallel computing units, such as those found in GP-GPUs and other clustered many-core accelerators. The result was a framework for cross-layer (i.e., across software stack) and hybrid (i.e., across hardware and software) resiliency. This enabled us to combine methods for correcting error and accepting error to devise a new method for approximate error correction across the hardware/software interface viamemoization. That is, ensuring safety of error-tolerance through a set of rules verified by a combination of design-time and runtime constraints. Spatial and temporal memorization, with the use of memristive memory blocks, significantly reduce the cost of resiliency and enhance the range of variability-induced timing errors that can be mitigated at very low cost.
Bio: Abbas Rahimi is currently a fifth year Ph.D. candidate in the Department of Computer Science and Engineering at the University of California, San Diego. He is working with Professor Rajesh Gupta and Professor Luca Benini. Since June 2010, he has also been with the Microelectronic Group at the University of Bologna and the Integrated Systems Laboratory at the Swiss Federal Institute of Technology Zurich. His research interests are in the massively parallel integrated architectures, approximate computing, resilient system design, design for robustness, embedded systems, and on-chip interconnections. Mr. Rahimi received the Best Paper Candidate at 50th IEEE/ACM Design Automation Conference. He received the B.S. degree in computer engineering from the School of Electrical and Computer Engineering at the University of Tehran, in March 2010.
Host: Gu-Yeon Wei
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